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A 10-bit, 200MS/s CMOS Pipeline ADC using new shared opamp architecture

Author(s): Hanie Ghaedrahmat | Khosrow Hajsadeghi

Journal: International Journal of VLSI Design & Communication Systems
ISSN 0976-1527

Volume: 3;
Issue: 6;
Start page: 1;
Date: 2013;
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Keywords: Analog to Digital converter (ADC) | opamp sharing | high speed | low power | memory effect | pipeline

A 10 bit opamp-sharing pipeline analog-to-digital converter (ADC) using a novel mirror telescopic operational amplifiers (opamp) with dual nmos differential inputs is presented. Reduction of power and area is achieved by completely merging the front-end sample-and-hold amplifier (SHA) into the first multiplying digital-to-analog converter (MDAC) using the proposed opamp. Transistors in the opamp are always biased in saturation to avoid increase of settling time due to opamp turn-on delays. The design targets 0.18um CMOS process for operation, at 200MS/s from a 1.8V supply. The simulation results show the SNDR and SFDR of 59.45dB and 68.69dB, respectively, and the power consumption of 35.04mW is achieved
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