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A 10 dBm-25 dBm, 0.363 mm2 Two Stage 130 nm RF CMOS Power Amplifier

Author(s): Shridhar R. Sahu | A. Y. Deshmukh

Journal: International Journal of VLSI Design & Communication Systems
ISSN 0976-1527

Volume: 4;
Issue: 5;
Start page: 107;
Date: 2013;
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Keywords: RF CMOS | PAE | Output Power | S-parameters | Matching Networks

This paper proposes a 2.4 GHz RF CMOS Power amplifier and variation in its main performanceparameters i.e, output power, S-parameters and power added efficiency with respect to change in supplyvoltage and size of the power stage transistor. The supply voltage was varied form 1 V to 5 V and the rangeof output power at 1dB compression point was found to be from 10.684 dBm to 25.08 dBm respectively.The range of PAE is 16.65 % to 48.46 %. The width of the power stage transistor was varied from 150 μmto 500 μm to achieve output power of range 15.47 dBm to 20.338 dBm. The range of PAE obtained here is29.085 % to 45.439 %. The total dimension of the layout comes out to be 0.714 * 0.508 mm2.
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