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22nm Ptm Model Low Power yet High Speed CMOS High K Metal Gate Strained Silicon Technology Inverter

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Author(s): Shobha S harma

Journal: International Journal of Engineering and Advanced Technology
ISSN 2249-8958

Volume: 1;
Issue: 5;
Start page: 87;
Date: 2012;
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ABSTRACT
This paper analysis four inverter configurationwith low power and high performance PTM models of ArizonaState University, USA at 22nm technology with High K metalgate strained silicon technology. The effect of stacked transistoris analysed to show the reduced average and peak powerdissipation. This stack effect is utilized in combination withforward biasing of a transistor to have low power but highspeed inverter without loosing the maximum and minimumvoltage swing at the output. Average power dissipated by lowpower stacked forward biased inverter is reduced by 4%compared to HP inverter. Peak power reduction is 64% in caseof this new inverter compared to traditional High Performanceinverter. The propagation delay is more compared to a HPinverter but is reduced by almost 18.2% compared to LowPower stacked inverter.
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