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A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error Correction Logic

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Author(s): P.Prasad Rao | Lal Kishore

Journal: International Journal of VLSI Design & Communication Systems
ISSN 0976-1527

Volume: 2;
Issue: 3;
Start page: 39;
Date: 2011;
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Keywords: ADC | 1.5 bit stage | CMFB | Pipeline | Redundancy bit removal algorithm

ABSTRACT
Use of pipelined ADCs is becoming increasingly popular both as stand alone parts and as embeddedfunctional units in SOC design. They have acceptable resolution and high speed of operation and can beplaced in relatively small area. The design is implemented in 0.18uM CMOS process. The design includes afolded cascode op-amp with a unity gain frequency of 200MHz at 88 deg. Phase margin and a dc gain of75dB. The circuit employs a built in sample and hold circuit and a three phase non-overlapping clock.
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