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AREA-EFFICIENT DESIGN OF SCHEDULER FOR ROUTING NODE OF NETWORK-ON-CHIP

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Author(s): Rehan Maroofi | V. N. Nitnaware | S. S. Limaye

Journal: International Journal of VLSI Design & Communication Systems
ISSN 0976-1527

Volume: 2;
Issue: 3;
Start page: 111;
Date: 2011;
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Keywords: Network-on-Chip | System-on-Chip | On-chip routing switch | Scheduler | iSLIP | Synthesis

ABSTRACT
Traditional System-on-Chip (SoC) design employed shared buses for data transfer among varioussubsystems. As SoCs become more complex involving a larger number of subsystems, traditional busbasedarchitecture is giving way to a new paradigm for on-chip communication. This paradigm is calledNetwork-on-Chip (NoC). A communication network of point-to-point links and routing switches is used tofacilitate communication between subsystems. The routing switch proposed in this paper consists of fourcomponents, namely the input ports, output ports, switching fabric, and scheduler. The scheduler design isdescribed in this paper. The function of the scheduler is to arbitrate between requests by data packets foruse of the switching fabric. The scheduler uses an improved round robin based arbitration algorithm. Dueto the symmetric structure of the scheduler, an area-efficient design is proposed by folding the scheduleronto itself, thereby reducing its area roughly by 50%.
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