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AREA OPTIMIZED FPGA IMPLEMENTATION FOR GENERATION OF RADAR PULSE COM-PRESSION SEQUENCES

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Author(s): P. Tirumala rao | P. Siva kumar | Y.V. Apparao | Y. Madhu babu

Journal: International Journal of VLSI Design & Communication Systems
ISSN 0976-1527

Volume: 2;
Issue: 3;
Start page: 151;
Date: 2011;
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Keywords: PULSE compression | Ternary sequence | Quaternary sequence | Polyphase sequence | Merit Factor | VLSI architecture | FPGA

ABSTRACT
Pulse compression technique is most widely used in radar and communication areas. Its implementationrequires an opti-mized and dedicated hardware. The real time implementation places several constraintssuch as area occupied, power con-sumption, etc. The good design needs optimization of these constraints.This paper concentrates on the design of optimized model which can reduce these. In the proposedarchitecture a single chip is used for generating the pulse compression se-quence like BPSk, QPSk, 6-PSKand other Polyphase codes. The VLSI architecture is implemented on the Field Programm-able Gate Array(FPGA) as it provides the flexibility of reconfigurability and reprogrammability .It was found that the proposedarchitecture has generated the pulse compression sequences efficiently while improving some of theparameters like area, power consumption and delay when compared to previous methods.
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