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Arithmetic Operations in Multi-Valued Logic

Author(s): Vasundara Patel k s | k s gurumurthy

Journal: International Journal of VLSI Design & Communication Systems
ISSN 0976-1527

Volume: 1;
Issue: 1;
Start page: 21;
Date: 2010;
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Keywords: Multiple-valued logic | Quaternary logic | Modulo-n addition and multiplication | Galois addition and multiplication.

This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternaryto binary and binary to quaternary converters are designed using down literal circuits. Negation inmodular arithmetic is designed with only one gate. Logic design of each operation is achieved byreducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in toconsideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulationresult of each operation is shown separately using Hspice.
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