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Asynchronous Hybrid Kogge-Stone Structure Carry Select Adder Based IEEE-754 Double-Precision Floating-Point Adder

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Author(s): Abhijith Kini G.

Journal: International Journal of Computer Science Issues
ISSN 1694-0784

Volume: 8;
Issue: 5;
Start page: 100;
Date: 2011;
Original page

Keywords: Double Precision Floating-Point | Hybrid | Kogge-Stone | Carry Select | Carry Look-Ahead | Adder | IJCSI

ABSTRACT
In this paper, the design and implementation of a generic fast asynchronous Hybrid Kogge-Stone Structure Carry Select based Adder (HKSS-CSA) is described in detail and its application in the design of asynchronous Double Precision Floating-Point Adder (DPFPA) is presented and the improved latency performance it provides is discussed. A detailed analysis in terms of maximum combinational delay, number of logic levels and logic resources used by both these adders is provided. The proposed HKSS-CSA adders performance is compared with a generic reference Carry Look-Ahead Adder (CLA) in terms of the above parameters. For the same set of inputs, the HKSS-CSA resulted in approximately 40% (32-bit) - 65% (128-bit) reduction in the number of logic levels, thereby improving the overall latency by a factor of 2 (32-bit) - 6 (128-bit) times compared to a CLA. A 64-bit instance of this HKSS-CSA was made use of in the design of an asynchronous DPFPA and its performance compared with a reference DPFPA which makes use of a CLA in the intermediate stage. The reference DPFPA had a maximum combinational delay of 36.25ns while the newly suggested DPFPA had a delay of 18.60ns for the same set of inputs, giving about 50% improvement in overall latency performance, which can be mainly attributed to the latency improvement provided by the HKSS-CSA.
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