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Avoiding Message-Dependent Deadlock in Network-Based Systems on Chip

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Author(s): Andreas Hansson | Kees Goossens | Andrei Rădulescu

Journal: VLSI Design
ISSN 1065-514X

Volume: 2007;
Date: 2007;
Original page

ABSTRACT
Networks on chip (NoCs) are an essential component of systems on chip (SoCs) and much research is devoted to deadlock avoidance in NoCs. Prior work focuses on the router network while protocol interactions between NoC and intellectual property (IP) modules are not considered. These interactions introduce message dependencies that affect deadlock properties of the SoC as a whole. Even when NoC and IP dependency graphs are cycle-free in isolation, put together they may still create cycles. Traditionally, SoCs rely solely on request-response protocols. However, emerging SoCs adopt higher-level protocols for cache coherency, slave locking, and peer-to-peer streaming, thereby increasing the complexity in the interaction between the NoC and the IPs. In this paper, we analyze message-dependent deadlock, arising due to protocol interactions between the NoC and the IP modules. We compare the possible solutions and show that deadlock avoidance, in the presence of higher-level protocols, poses a serious challenge for many current NoC architectures. We evaluate the solutions qualitatively, and for a number of designs we quantify the area cost for the two most economical solutions, strict ordering and end-to-end flow control. We show that the latter, which avoids deadlock for all protocols, adds an area and power cost of 4% and 6%, respectively, of a typical Æthereal NoC instance.
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