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Block-Level Logic Extraction from CMOS VLSILayouts

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Author(s): Inderpreet Bhasin | Joseph G. Tront

Journal: VLSI Design
ISSN 1065-514X

Volume: 1;
Issue: 3;
Start page: 243;
Date: 1994;
Original page

Keywords: Layout Verification | Logic Extraction | VLSI Design.
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