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Braun’s Multiplier Implementation using FPGA with Bypassing Techniques.

Author(s): Anitha R | Bagyaveereswaran V

Journal: International Journal of VLSI Design & Communication Systems
ISSN 0976-1527

Volume: 2;
Issue: 3;
Start page: 201;
Date: 2011;
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Keywords: Digital Signal Processing (DSP) | Field Programmable Gate Array (FPGA) | fast addition | Spartan-3E | truncated multiplier | Verilog HDL | Virtex-4 | Virtex-5 | Virtex – 6 Low power.

The developing an Application Specific Integrated Circuits (ASICs) will cost very high, the circuits shouldbe proved and then it would be optimized before implementation. Multiplication which is the basic buildingblock for several DSP processors, Image processing and many other. The Braun multipliers can easily beimplemented using Field Programmable Gate Array (FPGA) devices. This research presented thecomparative study of Spartan-3E, Virtex-4, Virtex-5 and Virtex-6 Low Power FPGA devices. Theimplementation of Braun multipliers and its bypassing techniques is done using Verilog HDL. We areproposing that adder block which we implemented our design (fast addition) and we compared the resultsof that so that our proposed method is effective when compare to the conventional design. There is thereduction in the resources like delay LUTs, number of slices used. Results are showed and it is verifiedusing the Spartan-3E, Virtex-4 and Virtex-5 devices. The Virtex-5 FPGA has shown the good performanceas compared to Spartan-3E and Virtex-4 FPGA devices.

Tango Jona
Tangokurs Rapperswil-Jona

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