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A BUS ENCODING TO REDUCE CROSSTALK NOISE EFFECT IN SYSTEM ON CHIP

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Author(s): J.Venkateswara Rao | A.V.N.Tilak

Journal: International Journal of VLSI Design & Communication Systems
ISSN 0976-1527

Volume: 2;
Issue: 2;
Start page: 110;
Date: 2011;
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Keywords: Crosstalk Encoding | SOC | parasitic | coupling Capacitance | micron | Forbidden Pattern free

ABSTRACT
This paper proposes a new bus coding scheme for reducing the crosstalk in System on chip(soc). Ascircuit geometries become smaller, wire interconnections become closer together and taller, thusincreasing the cross-coupling capacitance between nets. At the same time, parasitic capacitance to thesubstrate becomes less as interconnections become narrower, and cell delays are reduced as transistorsbecome smaller. With circuit geometries at 0.25 micron and above, substrate capacitance is usually thedominant effect. However, with geometries at 0.18 micron and below, the coupling capacitance betweennets becomes significant, making crosstalk analysis increasingly important for accurate timing analysis.We show experimentally that the proposed codes allow reducing crosstalk delay by at least 14% based onavailable data.
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