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C-Pack: A High-Performance Microprocessor Cache Compression Algorithm


Journal: International Journal of Soft Computing & Engineering
ISSN 2231-2307

Volume: 1;
Issue: 5;
Start page: 336;
Date: 2011;
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Keywords: Cache compression | effective system-wide compression ratio | hardware implementation | pair matching | parallel compression.

Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memory. Accessing off-chip memory generally takes an order of magnitude more time than accessing on-chip cache, and two orders of magnitude more time than executing an instruction. Computer systems and microarchitecture researchers have pro- posed using hardware data compression units within the memory hierarchies of microprocessors in order to improve performance, energy efficiency, and functionality. Furthermore, as we show in this paper, raw compression ratio is not always the most important metric. In this work, we present a lossless compression algorithm that has been designed for fast on-line data compression, and cache compression in particular. The algorithm has a number of novel features tailored for this application, including combining pairs of compressed lines into one cache line and allowing parallel compression of multiple words while using a single dictionary and without degradation in compression ratio. We reduced the proposed algorithm to a register transfer level hardware design, permitting performance, power consumption, and area estimation. Permitting performance, power consumption, and area estimation. Experiments comparing our work to previous work are described.
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