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CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations

Author(s): Eitan N. Shauly

Journal: Journal of Low Power Electronics and Applications
ISSN 2079-9268

Volume: 2;
Issue: 1;
Start page: 1;
Date: 2012;
Original page

Keywords: low leakage | low power | layout optimization | transistor scaling | leakage-related-stressors | design-aware leakage reduction

Power reduction in CMOS platforms is essential for any application technology. This is a direct result of both lateral scaling—smaller features at higher density, and vertical scaling—shallower junctions and thinner layers. For achieving this power reduction, solutions based on process-device and process-integration improvements, on careful layout modification as well as on circuit design are in use. However, the drawbacks of these solutions, in terms of greater manufacturing complexity (and higher cost) and speed degradation, call for “optimized” solutions. This paper reviews the issues associated with transistor scaling and related solutions for leakage and power reduction in terms of topological design rules and layout optimization for digital and analog transistors. For standard cells and SRAMs cells, leakage aware layout optimization techniques considering transistor configuration, stressors, line-edge-roughness and more are presented. Finally, different techniques for leakage and power reduction at the circuit level are discussed.
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