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CMOS Low Power Cell Library for Digital Design

Author(s): Kanika Kaur | Arti Noor

Journal: International Journal of VLSI Design & Communication Systems
ISSN 0976-1527

Volume: 04;
Issue: 03;
Start page: 43;
Date: 2013;
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Keywords: Cell Library | Dynamic Power | Subthreshold

Historically, VLSI designers have focused on increasing the speed and reducing the area of digital systems.However, the evolution of portable systems and advanced Deep Sub-Micron fabrication technologies havebrought power dissipation as another critical design factor. Low power design reduces cooling cost andincreases reliability especially for high density systems. Moreover, it reduces the weight and size ofportable devices. The power dissipation in CMOS circuits consists of static and dynamic components. Sincedynamic power is proportional to V2dd and static power is proportional to Vdd, lowering the supply voltageand device dimensions, the transistor threshold voltage also has to be scaled down to achieve the requiredperformance.In case of static power, the power is consumed during the steady state condition i.e when there are noinput/output transitions. Static power has two sources: DC power and Leakage power. Consecutively tofacilitate voltage scaling without disturbing the performance, threshold voltage has to be minimized.Furthermore it leads to better noise margins and helps to avoid the hot carrier effects in short channeldevices. In this paper we have been proposed the new CMOS library for the complex digital design usingscaling the supply voltage and device dimensions and also suggest the methods to control the leakagecurrent to obtain the minimum power dissipation at optimum value of supply voltage and transistorthreshold. In this paper CMOS Cell library has been implemented using TSMC (0.18um) and TSMC(90nm) technology using HEP2 tool of IC designing from Mentor Graphics for various analysis andsimulations.
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