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Comparative study of Braun’s Multiplier Using FPGA Devices

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Author(s): Anitha R, | Bagyaveereswaran V

Journal: International Journal of Engineering Science and Technology
ISSN 0975-5462

Volume: 3;
Issue: 6;
Start page: 4785;
Date: 2011;
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Keywords: ASIC | FPGA | Bypassing Technique | Xilinx

ABSTRACT
The development cost for ASIC are high, algorithms should be verified and optimized before implementation. To decrease computational delay and improve resource utilization, bypassing techniques are beapplied and braun-arhitectured multiplier is compared with its architectural modification i.e. Column-bypassing and Row-bypassing architectures and the full adder structure has been replaced by the fast adder. The architectures have been implemented on Spartan 3E, Virtex 5 and Virtex 6 LowerPower. Virtex 5 showed the best performance whereas column-bypassed multiplier has the best performance among the three architectures using Xilinx ISE and Verilog HDL.
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