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A Comparative Study of Ultra-Low Voltage Digital Circuit Design

Author(s): Aaron Arthurs | Justin Roark | Jia Di

Journal: International Journal of VLSI Design & Communication Systems
ISSN 0976-1527

Volume: 3;
Issue: 3;
Start page: 1;
Date: 2012;
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Keywords: Ultra-Low Voltage | Asynchronous Logic | Delay-Insensitive | Schmitt-Triggered | Silicon-on-Insulator

Ultra-low voltage digital circuit design is an active research area, especially for portable applications such as wearable electronics, intelligent remote sensors, implantable medical devices, and energy-harvesting systems. Due to their application scenarios and circuit components, two major goals for these systems are minimizing energy consumption and improving compatibility with low-voltage power supplies and analog components. The most effective solution to achieve these goals is to reduce the supply voltage, which,however, raises the issue of operability. At ultra-low supply voltages, the integrity of digital signals degrades dramatically due to the indifference between active and leakage currents. In addition, the system timing becomes more unpredictable as the impact of process and supply voltage variations being more significant at lower voltages. This paper presents a comparative study among three techniques for designing digital circuits operating at ultra-low voltages, i.e., Schmitt-triggered gate structure, delayinsensitive asynchronous logic, and Fully-Depleted Silicon-on-Insulator technology. Results show that despite the tradeoffs, all eight combinations of these techniques are viable for designing ultra-low voltage circuits. For a given application, the optimum circuit design can be selected from these combinations based on the lowest voltage, the dynamic range, the power budget, the performance requirement, and the available semiconductor process node.
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