**Author(s): ** Chiranjeevi Oguri |

C. Rambabu |

S.M.A. Naveed**Journal: ** International Journal of Computer & Electronics Research ISSN 2320-9348

**Volume: ** 2;

**Issue: ** 3;

**Start page: ** 166;

**Date: ** 2013;

Original page**Keywords: ** Trellis-coded Modulation |

Viterbi decoder |

Power reduction**ABSTRACT**

Trellis-coded Modulation is used in band limited communication systems and its efficiency improves coding gain by combining modulation and forward error adjustment coding in one process. Even though the constraint length of the convolution code is moderate, Trellis coded modulation method which is used in numerous band-width-efficient systems employs a high-rate convolution code, leading to a high complication of the Viterbi decoder for the Trellis coded modulation decoder. The Viterbi decoder is the dominant module in a Trellis coded modulation decoder, in terms of power consumption. Power reduction in Viterbi decoder could be achieved by reducing the number of states such as reduced-state sequence decoding, M-algorithm, T-algorithm or by over-scaling the supply voltage. An add-compare-select unit architecture based on pre-computation for Viterbi decoder incorporating T-algorithm, which capably improves the clock speed of a Viterbi decoder with T-algorithm for a rate-3/4 code, is proposed. T-algorithm which only searches for the optimal path metric that is, the minimum value or the maximum value of all path metrics, and has been shown to be very efficient in reducing the power consumption is more commonly used. T -algorithm requires extra computation in the add-compare-select unit loop for calculating the optimal path metric and puncturing states. A straight-forward implementation of T-algorithm will dramatically reduce the decoding speed. The key point of improving the clock speed of T-algorithm is to quickly ﬁnd the optimal path metric.

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