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Cost-Effective Video Filtering Solution for Real-Time Vision Systems

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Author(s): Fischer Viktor | Lukac Rastislav | Martin Karl

Journal: EURASIP Journal on Advances in Signal Processing
ISSN 1687-6172

Volume: 2005;
Issue: 13;
Start page: 568069;
Date: 2005;
Original page

Keywords: VHDL implementation | FPLD | bit-serial approach | pipelined solution | video filtering and enhancement | nonlinear adaptive filter design

ABSTRACT
This paper presents an efficient video filtering scheme and its implementation in a field-programmable logic device (FPLD). Since the proposed nonlinear, spatiotemporal filtering scheme is based on order statistics, its efficient implementation benefits from a bit-serial realization. The utilization of both the spatial and temporal correlation characteristics of the processed video significantly increases the computational demands on this solution, and thus, implementation becomes a significant challenge. Simulation studies reported in this paper indicate that the proposed pipelined bit-serial FPLD filtering solution can achieve speeds of up to 97.6 Mpixels/s and consumes 1700 to 2700 logic cells for the speed-optimized and area-optimized versions, respectively. Thus, the filter area represents only 6.6 to 10.5% of the Altera STRATIX EP1S25 device available on the Altera Stratix DSP evaluation board, which has been used to implement a prototype of the entire real-time vision system. As such, the proposed adaptive video filtering scheme is both practical and attractive for real-time machine vision and surveillance systems as well as conventional video and multimedia applications.
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