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Delay-Power Performance Comparison of Multipliers in VLSI Circuit Design

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Author(s): Sumit Vaidya | Deepak Dandekar

Journal: International journal of Computer Networks & Communications
ISSN 0975-2293

Volume: 2;
Issue: 4;
Start page: 47;
Date: 2010;
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Keywords: Multiplier | Vedic Mathematics | VLSI design

ABSTRACT
A typical processor central processing unit devotes a considerable amount of processing time inperforming arithmetic operations, particularly multiplication operations. Multiplication is one of thebasic arithmetic operations and it requires substantially more hardware resources and processing timethan addition and subtraction. In fact, 8.72% of all the instruction in typical processing units ismultiplication. In this paper, comparative study of different multipliers is done for low power requirementand high speed. The paper gives information of “Urdhva Tiryakbhyam” algorithm of Ancient IndianVedic Mathematics which is utilized for multiplication to improve the speed, area parameters ofmultipliers. Vedic Mathematics suggests one more formula for multiplication of large number i.e.“Nikhilam Sutra” which can increase the speed of multiplier by reducing the number of iterations.

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