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Design of Digital FIR Filter Based on Dynamic Distributed Arithmetic Algorithm

Author(s): T. Vigneswaran | P. Subbarami Reddy

Journal: Journal of Applied Sciences
ISSN 1812-5654

Volume: 7;
Issue: 19;
Start page: 2908;
Date: 2007;
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Keywords: multiplier less arithmetic unit | FIR filter | Distributed arithmetic | high speed | VLSI

This research presents a method for implementing high speed Finite Impulse Response (FIR) filters using just adders, Look Up Tables (LUTs) and shifters. The extensive use of a Dynamic Distributed Arithmetic (DDA) algorithm eliminates the multiplier unit which requires more number of adders. Xilinx Spartan III devices is used for optimization. It is observed that up to 56.75% reduction in the number of slices, upto 75% reduction in flip flops and up to 53.2% reduction in the number of LUTs is achieved. The speed of the DDA is improved by 31%.
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