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Design and Implementation of Floating Point Multiplier for Better Timing Performance

Author(s): B.Sreenivasa Ganesh,J.E.N.Abhilash, G. Rajesh Kumar

Journal: International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
ISSN 2278-1323

Volume: 1;
Issue: 7;
Start page: 130;
Date: 2012;
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Keywords: Floating point | multiplication | VHDL | Spartan-3 FPGA | Pipelined architecture | Timing Analyzer | IEEE Standard 754

IEEE Standard 754 floating point is the most common representation today for real numbers on computers. This paper gives a brief overview of IEEE floating point and its representation. This paper describes a single precision floating point multiplier for better timing performance. The main object of this paper is to reduce the power consumption and to increase the speed of execution by implementing certain algorithm for multiplying two floating point numbers. In order to design this VHDL is the hardware description language is used and targeted on a Xilinx Spartan-3 FPGA. The implementation’s tradeoffs are area speed and accuracy. This multiplier also handles overflow and underflow cases. For high accuracy of the results normalization is also applied. By the use of pipelining process this multiplier is very good at speed and accuracy compared with the previous multipliers. This pipelined architecture is described in VHDL and is implemented on Xilinx Spartan 3 FPGA. Timing performance is measured with Xilinx Timing Analyzer. Timing performance is compared with standard multipliers.
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