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Design and Implementation of A Memory For Joint Improvement Of Error Tolerance And Access Efficiency

Author(s): Kavya Cheraukula | Chowdam Venkata Sudhakar

Journal: International Journal of Engineering and Advanced Technology
ISSN 2249-8958

Volume: 1;
Issue: 5;
Start page: 128;
Date: 2012;
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Keywords: cache memory | ECC | soft error | URL.

The on-chip memory becomes increasingly exposed to the dual challenges of device-level reliability degradation and architecture-level performance gap. We propose to exploit the inherent memory soft redundancy for on-chip memory design. Due to the mismatch between fixed cache line size and runtime variations in memory spatial locality, many irrelevant data are fetched into the memory thereby wasting memory spaces. The proposed soft-redundancy allocated memory detects and utilizes these memory spaces for jointly achieving efficient memory access and effective error control. We design an CRC & ECC with error correction techniques by making use of standard Ethernet (004C11DB7H) polynomial and compare with each other, which will be implemented in FPGA proposed system design which take care of the Cache and memory by re-checking the cache when a miss is identified and help in effective functionality of the system and finally we compare which method will give good results in terms of cost and reliability.
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