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Design and Implementation of Simultaneous Shield And Repeater Insertion for On-chip Interconnects

Author(s): M. Surendra Goud Mr. Y. Sreenivas Goud

Journal: International Journal of Electronics Communication and Computer Engineering
ISSN 2249-071X

Volume: 3;
Issue: 1;
Start page: 156;
Date: 2012;
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Keywords: Optimization | Power delay | Noise | Repeater insertion | Resources | Shielding

A Resource based optimization is a new approach for high performance integrated circuits. The method is applied to simultaneous shield and repeater insertion, resulting in minimum coupling noise under power, delay, and area constraints Repeater insertion is a well known design technique to reduce the delay required to propagate a signal along a line. Shielding inserts an additional line between a victim line and an aggressor line. Finally placing a shield beside and inserting repeaters along a victim line and are chosen to exemplify the resource based optimization process. In the active shielding architecture shield driving circuits as 4:1 multiplexer, full adder, multipliers are inserted. The power consumption of active shielding architecture is observed to be approximately 20% less compare to passive shielding architecture. The main aim of this is minimize the coupling noise under power, delay, and area constraints
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