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Design of Low Power Sigma Delta ADC

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Author(s): Mohammed Arifuddin Sohel | K. Chenna Kesava Reddy | Syed Abdul Sattar

Journal: International Journal of VLSI Design & Communication Systems
ISSN 0976-1527

Volume: 3;
Issue: 4;
Start page: 67;
Date: 2012;
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Keywords: Discrete Time Sigma Delta Modulation | Low Power design | Oversampling | CIC Decimation Filter

ABSTRACT
A Low power discrete time sigma delta ADC consisting of a second order sigma delta modulator and third order Cascaded Integrated Comb (CIC) filter is proposed. The second order modulator is designed to work at a signal band of 20K Hz at an oversampling ratio of 64 with a sampling frequency of 2.56 MHz. It achieves a signal to noise ratio of 85.2dB and a resolution of 14 bits. The CIC digital filter is designed to implement a decimation factor of 64, operating at a maximum sampling frequency of 2.56 MHz. A second order sigma delta modulator is implemented in 0.18micron CMOS technology using full custom design and the third order digital CIC decimation filter is implemented in verilog HDL. The complete Sigma Delta ADC, consisting of analog block of second order modulator and digital block of decimator consumes a total power 1.96mW.
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