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Design of More Secured on chip Bus OCP with FPGA Implementation

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Author(s): G.Mamatha# , S.Mrudula

Journal: International Journal of Engineering Trends and Technology
ISSN 2231-5381

Volume: 4;
Issue: 6;
Start page: 2608;
Date: 2013;
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Keywords: Soc | O.C.P | AMBA | AXI

ABSTRACT
The implementation of a huge scale SoC(System-onchip) is becoming difficult task not only due to its complexity, but also the design of a more amount of IPs. A consensus interface protocol for IP cores is becoming significant and even predictable for a successful SoC establishment. OCP, with its candidness, concerted, not-for-profit nature, and inherent large industry member base, is quickly becoming a feasible and preferable solution over a close or an in-house standard. In this project; well-defined interface standard, the Open Core Protocol (OCP), and focus on the design of the internal bus architecture. We develop an efficient bus architecture to support most advanced bus properties defined in OCP, including burst transactions, lock transactions, pipelined transactions, and out-of-order transactions. on-chip bus with transaction level modelling for the consideration of design flexibility and fast simulation speed is presented in this project.
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