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DESIGN OF MULTI BIT LFSR PNRG AND PERFORMANCE COMPARISON ON FPGA USING VHDL

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Author(s): Amit Kumar Panda | Praveena Rajput | Bhawna Shukla

Journal: International Journal of Advances in Engineering and Technology
ISSN 2231-1963

Volume: 3;
Issue: 1;
Start page: 566;
Date: 2012;
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Keywords: LFSR | FPGA | PRNSG | VHDL

ABSTRACT
The main purpose of this paper is to study the FPGA implementation and performance analysis of 8, 16, and32 bit LFSR pseudo random number generator system. We have used FPGA to explain how FPGA’s ease the hardware implementation part of communication systems. The analysis is conceded out to find number of gates, memory and speed requirement in FPGA as the number of bits is increased. The comparative study of 8, 16 and 32 bit LFSR on FPGA is shown here to understand the on chip verification. Recently the field programmable gate arrays have enjoyed wide spread use due to several advantages related to relatively high gate density, short design cycle and low cost. The greatest advantage of FPGA’s are flexibility that we reconfigured the design many times and check the results and verify it on-chip for comparing with others PN sequence generators. The logic of PN Sequence Generator presented here can be changed any time, if we want a PN generator of more length all we need to do is change the number of shift register and adjust the taps. In this paper we have used one XOR operation for taping. Also we can use XNOR operation for taping. By increasing the number of tapping we can generate more randomness in the sequence.
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