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Design of a Parallel Sampling Encoder for Analog to Information (A2I) Converters: Theory, Architecture and CMOS Implementation

Author(s): Thomas S. Murray | Philippe O. Pouliquen | Andreas G. Andreou

Journal: Electronics (Basel)
ISSN 2079-9292

Volume: 2;
Issue: 1;
Start page: 57;
Date: 2013;
Original page

Keywords: analog to information converter | sub-Nyquist sampling | compressive sensing | parallel ADCs

We discuss the architecture and design of parallel sampling front ends for analog to information (A2I) converters. As a way of example, we detail the design of a custom 0.5 m CMOS implementation of a mixed signal parallel sampling encoder architecture. The system consists of configurable parallel analog processing channels, whose output is sampled by traditional analog-to-digital converters (ADCs). The analog front-end modulates the signal of interest with a high-speed digital chipping sequence and integrates the result prior to sampling at a low rate. An FPGA is employed to generate the chipping sequences and process the digitized samples.
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