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Design of Vedic Multiplier for Digital Signal Processing Applications

Author(s): R.Naresh Naik1 , P.Siva Nagendra Reddy2 , K. Madan Mohan

Journal: International Journal of Engineering Trends and Technology
ISSN 2231-5381

Volume: 4;
Issue: 7;
Start page: 3025;
Date: 2013;
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Keywords: Q-format | Urdhava Tiryakbhyam | Vedic Mathematics | Fractional fixed point.

Multiplier is one of the most important part in any processor speed which improves the speed of the operation like in special application processors like Digital Signal Processor (DSPs).To Increase the speed of operation we should take care of the precision previously we used the floating point multipliers which were consume more silicon area and take more clock frequency than fixed point (Qformat) multipliers. Now we propose a method which is faster multiplication technique by using Vedic mathematics formula Urdhava Tiryakbhyam method which means vertically and cross wire. All the operations in Vedic multiplier were executed concurrently and also we will get the output same as input bit length so Vedic multiplier is time, space and power efficient .The coding is done for 16-bit (Q-15) and 32-bit (Q-31) fractional fixed point multiplications using Verilog and synthesized using Xilinx ISE version 14.3. Further the speed comparisons of this multiplier with Normal Booth multiplier were presented. The results clearly show that our Urdhava Tiryakbhyam multiplier can have great amount of impact on the DSP applications to improve the execution speed of the DSP processors when compared to other multipliers.

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