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A Digital Auto-Zeroing Circuit to Reduce Offset in Sub-Threshold Sense Amplifiers

Author(s): Peter Beshay | Joseph F. Ryan | Benton H. Calhoun

Journal: Journal of Low Power Electronics and Applications
ISSN 2079-9268

Volume: 3;
Issue: 2;
Start page: 159;
Date: 2013;
Original page

Keywords: offset compensation | SRAM | sense amplifier | auto-zeroing

Device variability in modern processes has become a major concern in SRAM design leading to degradation of both performance and yield. Variation induced offset in the sense amplifiers requires a larger bitline differential, which slows down SRAM access times and causes increased power consumption. The effect aggravated in the sub-threshold region. In this paper, we propose a circuit that reduces the sense amp offset using an auto-zeroing scheme with automatic temperature, voltage, and aging tracking. The circuit enables flexible tuning of the offset voltage. Measurements taken from a 45 nm test chip show the circuit is able to limit the offset to 20 mV. A 16kB SRAM is designed using the auto-zeroing circuit for the sense amps. The reduction in the total read energy and delay is reported for various configurations of the memory.
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