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Efficient Hardware/Software Implementation of LPC Algorithm in Speech Coding Applications

Author(s): Mohamed Atri | Fatma Sayadi | Wajdi Elhamzi | Rached Tourki

Journal: Journal of Signal and Information Processing
ISSN 2159-4465

Volume: 03;
Issue: 01;
Start page: 122;
Date: 2012;
Original page

Keywords: Linear Predictive Coding | System on Programmable Chip | FPGA | Co-Design

The LPC “Linear Predictive Coding” algorithm is a widely used technique for voice coder. In this paper we present different implementations of the LPC algorithm used in the majority of voice decoding standard. The windowing/autocorrelation bloc is implemented by three different versions on an FPGA Spartan 3. Allowing the possibility to integrate a Microblaze processor core a first solution consists of a pure software implementation of the LPC using this core RISC processor. Second solution is a pure hardware architecture implemented using VHDL based methodology starting from description until integration. Finally, the autocorrelation core is then proposed to be implemented using hardware/software (HW/SW) architecture with the existing processor. Each architecture performances are compared for different data lengths.
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