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Energy, Throughput and Area Evaluation of Regular and Irregular Network on Chip Architectures

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Author(s): 1Umamaheswari S | Rajapaul Perinbam J

Journal: International Journal of Distributed and Parallel Systems
ISSN 2229-3957

Volume: 2;
Issue: 5;
Start page: 47;
Date: 2011;
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Keywords: Network on Chip (NoC) | Irregular topology | performance comparison | Topology generation | Throughput | Energy | silicon area.

ABSTRACT
Network-on-chip has been proposed in System-on-Chip to achieve high performance, reusability andscalability through generating application specific topologies. Application specific topologies areirregular in structure and take into account certain factors like communication weight, area and energyconstraints while building up the topology. Regular topologies like 2D mesh, spidergon are morestructured and are built not considering much about the system characteristics and other requirements.Consequently the throughput, power utilization and silicon area vary depending on the topology. Thispaper provides an evaluation of the performance measures of the regular topological structures andirregular application specific NoC.
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