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Fast Switching Fractional-N Frequency Synthesizer Architecture Using TDTL

Author(s): Mahmoud A. AL-QUTAYRI | Saleh R. AL-ARAJI | Abdulrahman Al-HUMAIDAN

Journal: International Journal of Communications, Network and System Sciences
ISSN 1913-3715

Volume: 02;
Issue: 09;
Start page: 879;
Date: 2009;
Original page

Keywords: Fractional | Synthesizer | Time Delay Tanlock Loop | Register Adaptation

This paper presents an efficient indirect fractional frequency synthesizer architecture based on the time delay digital tanlock loop. The indirect type frequency synthesis systems incorporate a low complexity high performance adaptation mechanism that enables them to remain in a locked state following the division process. The performance of the proposed fractional-N synthesizer under various input conditions is demonstrated. This includes sudden changes in the system input frequency as well as the injection of noise. The results of the extensive set of tests indicate that the fractional-N synthesizer, proposed in this work, performs well and is capable of achieving frequency divisions with fine resolution. The indirect frequency synthesizer also has a wide locking range and fast switching response. This is reflected by the system ability to regain its lock in response to relatively large variations in the input frequency within a few samples. The overall system performance shows high resilience to noise as reflected by the mean square error results.
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