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Fault Modeling of Combinational and Sequential Circuits at Register Transfer Level

Author(s): M.S.Suma | K.S.Gurumurthy

Journal: International Journal of VLSI Design & Communication Systems
ISSN 0976-1527

Volume: 2;
Issue: 4;
Start page: 61;
Date: 2012;
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Keywords: Automatic test pattern generation (ATPG) | fault coverage | fault simulation | stuck-at fault | RTL

As the complexity of Very Large Scale Integration (VLSI) is growing, testing becomes tedious and tougher. As of now fault models are used to test digital circuits at the gate level or below that level. By using fault models at the lower levels, testing becomes cumbersome and will lead to delays in the design cycle. In addition, developments in deep submicron technology provide an opening to new defects. We must develop efficient fault detection and location methods in order to reduce manufacturing costs and time to market. Thus there is a need to look for a new approach of testing the circuits at higher levels to speed up the design cycle. This paper proposes on Register Transfer Level (RTL) modeling for digital circuits and computing the fault coverage. The result obtained through this work establishes that the fault coverage with the RTL fault model is comparable to the gate level fault coverage.
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