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FPGA Based Hardware Efficient Digital Decimation Filter for Σ-Δ ADC

Author(s): Subir Kr. Maity | Himadri Sekhar Das

Journal: International Journal of Soft Computing & Engineering
ISSN 2231-2307

Volume: 1;
Issue: 6;
Start page: 129;
Date: 2012;
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Keywords: Oversampling | quantization | SNR | Sigma-Delta | Decimation | CIC Filter | FPGA.

This paper focuses on the design of a FPGA based off chip digital decimation filter for single bit sigma-delta A/D converter with medium oversampling ratio for the processing of audio signal. A second-order single-stage sigma-delta (Σ-Δ) modulator with single bit quantizer with oversampling ratio 96 from FALCON Instrument is used in this work as a reference modulator. To reduce hardware requirement, multiplier less FIR filter architecture used. Total three cascaded comb type filter are used for decimation and filtering purpose. Those filters are designed and simulated with MATLAB Filter Design Toolbox and finally mapped into XILINX SPARTAN-II XC2S50PQ208 series FPGA. The overall ADC gives 14 bit resolution.

Tango Jona
Tangokurs Rapperswil-Jona

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