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FPGA Based An Optimized Design of 3-Phase Induction Machine Speed Control

Author(s): Tole Sutikno

ISSN 1693-6930

Volume: 06;
Issue: 2;
Start page: 83;
Date: 2008;
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Keywords: FPGA | Induction Motor | MAX+Plus Baseline | Inverter | SPWM

The problem of FPGA based implementation of PWM signal generating system is solution of transformation to digital gate logic space. These stages are done with sampling, quantizing and coding. Higher resolution of sampling and carrier frequency, so result of PWM generating is better, but it required more digital gate. The aim of this research is to optimize the previous design of adjustable speed drive of three-phase induction motor control through the improving of sampling resolution and higher carrier frequency, and the simplification of digital gate required using Quine Mc Cluskey method. The research result shows that the design of optimized SPWM generating signal can be realized in ACEXIK FPGA hardware-logic to drive inverter as speed control of three phase induction motor while requiring 1629 logic cells. Changing the modulation index and frequency can be used to vary speed of three phase induction machine. In this research, the system have been verified at modulation index variation and frequency setting 3-50 Hz. It shows adequate to control three phase induction motor speed in range 117-1468 rpm.
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