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A FPGA Implementation of a RISC Processor for Computer Architecture

Author(s): Vijay R. Wadhankar | Vaishali Tehre

Journal: International Journal of Computer Applications
ISSN 0975-8887

Volume: ncipet;
Issue: 1;
Date: 2012;
Original page

This paper is concerned with the design and implementation of a 32bit Reduced Instruction Set Computer (RISC) processor on a Field Programmable Gate Arrays (FPGAs). We are designing the processor with VHDL and the simulation using Altera Quartus Plus2, and we will implement on Altera cyclone II in FPGA.The test bench waveforms for the different parts of the processor are presented and the system architecture is demonstrated.
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