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FPGA Implementation of Viterbi Decoder

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Author(s): ANUBHUTI KHARE | MANISH SAXENA | JAGDISH PATEL

Journal: International Journal of Computer Applications
ISSN 0975-8887

Volume: iccia;
Issue: 1;
Date: 2012;
Original page

Keywords: Convolutional encoder | Viterbi decoder | FPGA | Spartan XC3S400A FPGA | FEC (Forward Error Correction) | Path memory | Register Exchange

ABSTRACT
The main goal of this paper was resource-optimized implementation of the decoder on the target platform. It is well known that data transmissions over wireless channels are affected by attenuation, distortion, interference and noise, which affect the receiver's ability to receive correct information. Convolutional encoding with Viterbi decoding is a powerful method for forward error correction. It has been widely deployed in many wireless communication systems to improve the limited capacity of the communication channels. In this paper, we present a Spartan XC3S400A field-programmable gate array implementation of Viterbi Decoder with a constraint length of 3 and a code rate of 1/3. The Viterbi Decoder is compatible with many common standards, such as DVB, 3GPP2, 3GPP LTE, IEEE 802.16, Hiperlan, and Intelsat IESS-308/309.
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