Academic Journals Database
Disseminating quality controlled scientific knowledge

FTL based 4Stage CLA Adder Design with Floating Gates

ADD TO MY LIST
 
Author(s): P.H.S.T. Murthy | K. Chaitanya | M.Murali Krishna | Malleswara Rao.V

Journal: International Journal of Computer Applications
ISSN 0975-8887

Volume: 17;
Issue: 6;
Start page: 1;
Date: 2011;
Original page

Keywords: Mirror adder circuit | MIFG | FTL | CMOS adder

ABSTRACT
Low-voltage and low-power circuit structures are substantive for almost all mobile electronic gadgets which generally have mixed mode circuit structures embedded with analog sub-sections. Using the reconfigurable logic of multi-input floating gate MOSFETs, 4-bit full adder has been designed for 1.1V operation. [1],[2] Multi-input floating gate (MIFG) transistors have been anticipating in realizing the increased functionality on a chip. A multi-input floating gate MOS transistor accepts multiple inputs signals, calculates the weighted sum of all input signals and then controls the ON and OFF states of the transistor. This enhances the transistor function to more than just switching. Implementing a design using multi-input floating gate MOSFETs brings down transistor count and number of interconnections. Here in this we have presented how to eliminate the propagate and generate signals this tends the design to become more efficient in area and power consumption by using feed through logic [8]. It has been included the four stage sum signal in FTL based adder with floating gates. The following information is about Carry look ahead adder circuit, tested with 45nm technology and is extended to ALU. The proposed circuit has been implemented in 45n-well CMOS technology.
Save time & money - Smart Internet Solutions      Why do you need a reservation system?