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Hardware-Resource Saving for Realization of Space Vector PWM Based on FPGA Using Bus-Clamping Technique

Author(s): Tole Sutikno

ISSN 1693-6930

Volume: 07;
Issue: 3;
Start page: 161;
Date: 2009;
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Keywords: bus-clamping | FPGA | SV-PWM | hardware-resource saving

The space vector pulse width modulation (SV-PWM) is more suitable and can increase the obtainable DC voltage utilization ratio very much compared to others PWM. Moreover, the modulation can obtain a better voltage total harmonic distortion (THD) factor. But until now, no studies that concern at hardware resources saving to realize SV-PWM based on FPGA. This paper proposes a new technique to realize SV-PWM based on FPGA. In order to get hardware resource saving, a simple technique to judge sectors, to calculate the firing pulses and to generate SV-PWM waveform without calculation of trigonometric function using bus-clamping technique is proposed. The technique has been implemented successfully based on APEX20KE FPGA to drive three phase induction machine 1.5 kW with low ripples in current and voltage, and has been shown that the proposed SVM method required the most minimum hardware resources compared to others research.
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