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A High-Speed High-Input Range Four Quadrant Analog Multiplier

Author(s): M. Mokarram | A. Khoei | Kh. Hadidi

Journal: Majlesi Journal of Electrical Engineering
ISSN 2008-1413

Volume: 4;
Issue: 1;
Start page: 13;
Date: 2010;
Original page

Keywords: Analog multiplier | four quadrant multiplier | defuzzification | CMOS‏

In this paper, a CMOS four quadrant multiplier based on flipped voltage follower and differential squaring circuit is presented. The proposed circuit has a compact architecture operating at a higher speed and a higher input voltage range compared to the previously presented structures. The transistors operate in the both saturation and ohmic regions. The circuit operates with a single supply voltage of 3.3V in a 0.35 µm CMOS technology where the total harmonic distortion (THD) is less than 1.1%, the linearity error is also less than 3%, -3db frequency is more than 180 MHz and the voltage input range is 3V . Simulation results are given to verify the functionality of the proposed multiplier.
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