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High Performance DCT Implementation using NEDA on FPGA

Author(s): Monika Zope | P. S. Mahajani

Journal: International Journal of Computer Applications
ISSN 0975-8887

Volume: iccia;
Issue: 1;
Date: 2012;
Original page

Keywords: DCT | Distributed Arithmetic | ASIC | NEDA Compression standards

DCT is at the core of the most current generation of image and video compression standards including JPEG, H.261, H.263+, MPEG-1, 2, 4. Distributed arithmetic approach increases the speed and accuracy while reducing cost metrics, power and area of the DSP applications. As reducing cost is attracting more and more attention in application-specific integrated circuit design, there is an increasing demand for more efficient DA paradigms which can eliminate the need of using ROMs. At the same time, it is capable of meeting throughput constraints. To meet this demand New Distributed Arithmetic (NEDA) approach is introduced. NEDA features implementation without the need of multipliers as in conventional MAC approach, and at the same time, without the need of ROM as in DA approach. NEDA can also expose redundancy existing in the adder array consisting of entries of 0 and 1. VHDL code for calculation of DCT is written and this code is synthesized and simulated. The simulation results are verified by comparing with MATLAB results.
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