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High Speed and Area Efficient 2D DWT Processor Based Image Compression

Author(s): Sugreev Kaur | Rajesh Mehra

Journal: Signal & Image Processing
ISSN 2229-3922

Volume: 1;
Issue: 2;
Start page: 22;
Date: 2011;
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Keywords: DCT | DFT | DWT | JPEG | FPGA.

This paper presents a high speed and area efficient DWT processor based design for Image Compressionapplications. In this proposed design, pipelined partially serial architecture has been used to enhance thespeed along with optimal utilization and resources available on target FPGA. The proposed model hasbeen designed and simulated using Simulink and System Generator blocks, synthesized with XilinxSynthesis tool (XST) and implemented on Spartan 2 and 3 based XC2S100-5tq144 and XC3S500E-4fg320target device. The results show that proposed design can operate at maximum frequency 231 MHz in caseof Spartan 3 by consuming power of 117mW at 28 degree/c junction temperature. The result comparisonhas shown an improvement of 15% in speed.
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