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HIGH SPEED BUTTERFLY ARCHITECTURE FOR CIRCULAR CONVOLUTION USING FNT WITH PARTIAL PRODUCT MULTIPLIER

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Author(s): HEMALATHA BANDARI | ALAHARI RADHIKA, | SAKE POTHALAIAH | Dr.K ASHOK BABU

Journal: International Journal of Engineering Science and Technology
ISSN 0975-5462

Volume: 3;
Issue: 1;
Start page: 479;
Date: 2011;
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Keywords: FNT | code conversion | butterfly operation | Diminished-1 representation | partial product multiplier

ABSTRACT
This paper presents high speed butterfly architecture for circular convolution based on FNT using partial product multipliers. FNT is ideally suited to digital computation requiring the order of N log N additions, subtractions and bit shifts, but no multiplications. In addition to being efficient, the FNT implementation is exact with no round off errors. Binary arithmetic permits the exact computation of FNT. This technique involves arithmetic in a binary code orresponding to the simplest one of a set of code translations from the normal binary representation of each integer in the ring of integer. In the first stage normal binary numbers are converted intotheir diminished-1 representation using code conversion (CC). Then butterfly operation (BO) is carried out to perform FNT and IFNT where the point wise multiplication is performed using modulo 2n+1 partial product multipliers. Thus modulo 2n+1 additions are avoided in the final stages of FNT and IFNT and hence execution delay is reduced compared to circular convolution done with FFT and DFT. This architecture has better throughput and involves less hardware complexity.

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