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High Speed FIR Filter Based on Truncated Multiplier and Parallel Adder

Author(s): Deepshikha Bharti | K. Anusudha

Journal: International Journal of Engineering Trends and Technology
ISSN 2231-5381

Volume: 5;
Issue: 5;
Start page: 243;
Date: 2013;
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Keywords: Digital signal processing(DSP ) | Truncated multiplier | Parallel adder | FIR filter | VLSI design.

High speed Finite Impulse Response filter (FIR) is designed using the concept of faithfully rounded truncated multiplier and parallel prefix adder. The bit width is also optimized without sacrificing the signal precision. A transposed form of FIR filter is implemented using an improved version of truncated multiplier and parallel prefix adder. Multiplication and addition is frequently required in Digital Signal Processing. Parallel prefix adder provides a high speed addition and the improved version of truncated multiplier also provides successive reduction in delay and the components used.
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