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High Speed Vedic Multiplier for Digital Signal Processors

Author(s): Pushpangadan Ramesh | Sukumaran Vineeth | Innocent Rino | Sasikumar Dinesh | Sundar Vaisak

Journal: IETE Journal of Research
ISSN 0377-2063

Volume: 55;
Issue: 6;
Start page: 282;
Date: 2009;
Original page

Keywords: Multiplier | Urdhva tiryakbhyam | Vedic mathematics

Digital signal processors (DSPs) are very important in various engineering disciplines. Fast multiplication is very -important in DSPs for convolution, Fourier transforms etc. A fast method for multiplication based on ancient Indian Vedic mathematics is proposed in this paper. Among the various methods of multiplications in Vedic mathematics, Urdhva tiryakbhyam is discussed in detail. Urdhva tiryakbhyam is a general multiplication formula applicable to all cases of multiplication. This algorithm is applied to digital arithmetic and multiplier architecture is formulated. This is a highly modular design in which smaller blocks can be used to build higher blocks. The coding is done in VHDL (very high speed integrated circuits hardware description language) and synthesis is done using Xilinx ISE series. The combinational delay obtained after synthesis is compared with the performance of the modified Booth Wallace multiplier which is a fast multiplier. This Vedic multiplier can bring about great improvement in DSP performance.

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