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High Throughput and Low Power NoC

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Author(s): Magdy A. El-Moursy | Mohamed Abdelgany

Journal: International Journal of Computer Science Issues
ISSN 1694-0784

Volume: 8;
Issue: 5;
Start page: 431;
Date: 2011;
Original page

Keywords: Network-on-Chip | Throughput | Power Dissipation | Topology | IJCSI

ABSTRACT
The High throughput architecture to achieve high performance Networks-on-Chip (NoC) is proposed. The throughput is increased by more than 38% while preserving the average latency. The area of the network switch is decreased by 18%. The required metal resources for the proposed architecture are increased by less than 10% as compared to the required metal resources for the conventional NoC architecture. Power characteristics of different high throughput NoC architectures are developed. The extra power dissipation of the proposed high throughput NoC is as low as 1% of the total power dissipation. Among different NoC topologies, High Throughput Butter Fat Tree (HTBFT) requires the minimum extra power dissipation and metal resources.
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