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Image Processor Using 3D-DWT as Part of Health Care Management System

Author(s): Kyung-Chang Park | Yun-Ki Hong | Sang-Jin Lee | Yeon-Ho Kim | Younggap You | Tae Won Cho | Kyoung-Rok Cho | Kamran Eshraghian

Journal: Journal of Systemics, Cybernetics and Informatics
ISSN 1690-4532

Volume: 7;
Issue: 5;
Start page: 91;
Date: 2009;
Original page

Keywords: Wavelet | Tsv | Image Compression | 3d-Dwt | Stacked Chip

This paper presents a low power and high speed 3D-DWT (three-dimensional discrete wavelet transform) architecture using stacked silicon dies for image compression of medical images. The interconnections of stacked chips are based on TSV (through silicon via) techniques. Its low power operation is due to short signal paths between layers. The area of 3D architecture is much smaller than that of 2D counterpart having the same performance. Each circuit/system layer can be optimized since it can be fabricated using a different technology. The 3D-DWT architecture consists of two processing elements (PE): a PE-odd (processing elements-odd) and a PE-even (processing elements-even) layer. Each layer processes pixel data derived from rows of the y axis, scanning from left to right side of the image data. Each layer operates in parallel yielding high throughput. The architecture can be used to compress medical image such as X-ray, MRI, NRI, CT and endoscopy by processing images frame by frame.
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