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Implementation of Matched Filter Based DSSS Digital GPS Receiver

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Author(s): V.SRIDHAR , T.NAGALAXMI , M.V BRAMHANANDA REDDY , M.SUNITHA RANI, M.RENUKA

Journal: International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
ISSN 2278-1323

Volume: 1;
Issue: 5;
Start page: 008;
Date: 2012;
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Keywords: GPS | DS-SS | AWGN | BPSK | FPGA

ABSTRACT
The Global Positioning System (GPS) is a satellite-based radio navigation system made up of a network of 24 satellites placed in an orbit by the US Department of Defense. GPS was originally intended for military applications, but now it is freely available to all. For anyone with a GPS receiver, the system will provide location and time. GPS provides accurate location and time information for an unlimited number of people in all weather, day and night, anywhere in the world. The GPS is made up of three parts: satellites orbiting the Earth; control and monitoring stations on Earth; and the GPS receivers owned by users. GPS satellites broadcast signals from space that are picked up and identified by GPS receivers. Each GPS receiver then provides three-dimensional location (latitude, longitude, and altitude) plus the time.GPS receivers incorporate Direct Sequence Spread Spectrum (DSSS) Techniques in their analysis. Traditionally, GPS receiver has been a chip set, consisting of two or more chips. With the advances in Integrated Circuit technology there is a trend towards a single chip solution, which is advantageous in many ways. Such a chip will help integration of a variety of applications from cell phones to wrist watches. It involves a high level of design integration. In this digital GPS signal receiver for a system on chip application is designed using VHDL aiming for FPGA synthesis. The digital GPS signal receiver takes data in digital form and performs the demodulation and dispreading of C/A code and outputs the navigational data bits. Various communication sub blocks such as C/A code generator, BPSK demodulator, correlator and threshold detector are modeled in VHDL and simulated using Modelsim. A four channel receiver is to be modeled and tested with four satellite signal mixed input added with AWGN (Additive White Gaussian Noise).All the modules functionality is verified with Modelsim simulator. Xilinx ISE tools are used for FPGA synthesis, Place & Route and timing analysis. Spartan 3E development board with Chipscope Pro tools is used for on chip analysis and debugging.
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