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Implementation of on Chip Data Bus Using Pre Emphasis Signaling

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Author(s): Pallavi Dedge | S.C. Badwaik

Journal: International Journal of Computer Applications
ISSN 0975-8887

Volume: ooc;
Issue: 1;
Date: 2012;
Original page

Keywords: interconnect | power dessiapation | delay | crosstalk | noise

ABSTRACT
This work describes a differential current-mode bus architecture based on driver pre-emphasis for on-chip global interconnects that achieves high-data rates while reducing bus power dissipation and improving signal delay latency. The 16-b bus core fabricated in 0.25- ? m complementary metaloxidesemi- conductor (CMOS) technology attains an aggregate signaling data rate of 64 Gb/s over 510-mm-long lossy interconnects. With a supply of 2.5 V, 25.548.7-mW power dissipation
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